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  1 nano power, push/pull output comparator isl28915 the isl28915 is a nano power comparator optimized for low-power applications. this device is designed for single-supply operation from 1.8v to 5.5v and typically consumes 500na of supply current. these devices also feature a push/pull output stage with rail-to-rail input and output swing (rrio), allowing for maximum battery usage. the combination of small footprint, low power, single supply, and rail-to-rail operation makes them ideally suited for all battery operated devices. the isl28915 features an enable pin and is offered in the 6 ld sot-23 package. the device operates over the -40c to +125c temperature range. features ? low active current . . . . . . . . . . . . . . . . . . . . . . . . . . 600na max ? low disable current. . . . . . . . . . . . . . . . . . . . . . . . . . 20na max ? propagation delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150s ? rail-to-rail input/output voltage range (rrio) ? wide supply range . . . . . . . . . . . . . . . . . . . . . . . . 1.8v to 5.5v ? operating temperature range. . . . . . . . . . .-40c to +125c applications ? battery-powered/portable systems ? telemetry and remote systems ? alarm and monitoring systems ? oscillator circuits ? window comparators ? threshold detectors/discriminators figure 1. typical application circuit figur e 2. supply current vs supply voltage isl28915 gnd v+ - + 5v in- in+ r l 2k ? v ref c 1 10f audio signal peak detector 360 380 400 420 440 460 480 500 520 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 supply voltage (v) r l = supply current (na) july 12, 2012 fn8343.0 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl28915 2 july 12, 2012 fn8343.0 ordering information part number (notes 1, 2, 3) part marking temp range (c) package tape & reel (pb-free) pkg. dwg. # ISL28915FH6Z-T7 bena -40c to +125c sot23-6 p6.064a notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb- free products are msl classified at pb-free peak reflow temperat ures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl28915 . for more information on msl please see techbrief tb363 . pin configuration isl28915fh6z (6 ld sot-23) top view 1 2 3 6 4 5 +- out gnd in+ v+ en in- pin descriptions isl28915fh6z (6 ld sot-23) pin name equivalent circuit description 1 out circuit 3 comparator output 2gndcircuit 4ground terminal 3 in+ circuit 1 comparator non-inverting input 4 in- circuit 1 comparator inverting input 5 en circuit 2 comparator enable pin; logic ?1? selects the enabled state: logic ?0? selects the disabled state 6 v+ circuit 4 positive power supply logic pin v+ gnd v+ gnd out circuit 3 circuit 1 circuit 2 v+ gnd capacitively coupled esd clamp circuit 4 in- v+ gnd in+
isl28915 3 july 12, 2012 fn8343.0 absolute maximum rating s thermal information maximum supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.75v supply turn-on voltage slew rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1v/s maximum differential input current . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma maximum differential input voltage . . . . . . . . . . . gnd - 0.5v to v+ + 0.5v min/max input voltage . . . . . . . . . . . . . . . . . . . . . . gnd - 0.5v to v+ + 0.5v output short-circuit duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . indefinite esd tolerance human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . . . 3kv machine model (tested per jesd22-a115-c) . . . . . . . . . . . . . . . . . . 150v charged device model (tested per jesd22-c110d) . . . . . . . . . . . . . 1kv latch-up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . . at +125c thermal resistance (typical) ja (c/w) jc (c/w) 6 ld sot-23 package (notes 4, 5) . . . . . . . 239 108 storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions ambient temperature range (t a ) . . . . . . . . . . . . . . . . . . .-40c to +125c operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125c supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8v to 5.5v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured with the component mounted on a high effective ther mal conductivity test board in free air. see tech brief tb379 f or details. 5. for jc , the ?case temp? location is taken at the package top center. electrical specifications v+ = 5v, gnd = 0v, v cm = 2.5v, t a = +25c, unless otherwise specified . boldface limits apply over -40c to +125c. parameter description conditions min (note 6) typ max (note 6) unit v os input offset voltage -2 -0.2 2 mv -2.5 2.5 mv i os input offset current -25 -3 25 pa -67 67 pa i b input bias current -31 1.2 31 pa -100 100 pa cmir common mode input range established by cmrr test 05 v cmrr common-mode rejection ratio v cm = 0.5v to 3.5v 72 98 db 70 db v cm = 0v to 5v 60 db psrr power supply rejection ratio v+ = 1.8v to 5.5v 77 100 db 70 db v out maximum output voltage swing r l terminated to v+/2 output low, r l = 10k ? 35 70 mv output high, r l = 10k ? 4.930 4.990 v i s,on supply current, enabled v en = v+ - 0.3v 500 600 na 900 na i s,off supply current, disabled v en = gnd + 0.3v 0.25 20 na 50 na v supply supply voltage range 1.8 5.5 v c in input capacitance 6pf enable input v enh enable pin high level v+ - 0.3 v v enl enable pin low level gnd + 0.3 v i en-h,l enable pin input current v en = 0v, 5v -80 2.2 80 na -200 200 na
isl28915 4 july 12, 2012 fn8343.0 timing t pd propagation delay low to high and high to low c l = 10pf, 20mv overdrive 150 260 s t r /t f output rise/fall time c l = 10pf 11 20 s note: 6. parameters with min and/or max limits are 100% tested at +25 c, unless otherwise specified. te mperature limits established by characterization and are not production tested. electrical specifications v+ = 5v, gnd = 0v, v cm = 2.5v, t a = +25c, unless otherwise specified . boldface limits apply over -40c to +125c. (continued) parameter description conditions min (note 6) typ max (note 6) unit typical performance curves figure 3. supply current vs supply voltage figure 4. propagation delay vs supply voltage (rising edge) figure 5. propagation delay vs supply voltage (falling edge) figure 6. propagation delay vs overdrive (rising edge) 360 380 400 420 440 460 480 500 520 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 supply voltage (v) r l = supply current (na) 0 50 100 150 200 250 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 overdrive = 20mv r l to gnd +propagation delay (s) r l to v+ r l = 10k ? supply voltage (v) overdrive = 100mv 160 140 120 40 0 20 60 80 100 180 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 supply voltage (v) -propagation delay (s) r l to gnd r l to v+ r l to v+ r l = 10k ? r l to gnd overdrive = 20mv overdrive = 100mv 0 100 200 300 400 500 600 1 10 100 1000 overdrive (mv) r l to gnd r l to v+ v+ = 2v v+ = 5v r l = 10k ? +propagation delay (s)
isl28915 5 july 12, 2012 fn8343.0 figure 7. propagation delay vs overdrive (falling edge ) figure 8. short circuit current vs supply voltage figure 9. enable threshold voltage vs supply voltage fig ure 10. enable to output delay time vs supply voltage figure 11. enable low to output turn-off time vs supply voltage figure 12. supply current vs temperature, v+, gnd = 2.5v typical performance curves (continued) 0 50 100 150 200 250 300 350 400 1 10 100 1000 overdrive (mv) -propagation delay (s) r l to gnd r l to v+ r l = 10k ? v+ = 2v v+ = 5v output current (ma) supply voltage (v) 5 10 15 20 25 30 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 sourcing sinking r l = 10 ? 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 e n a b l e t h r e s h o l d ( v ) supply voltage (v) 760 780 800 820 840 860 880 900 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 supply voltage (v) e n a b l e t i m e ( s ) 1 2 3 4 5 6 7 8 9 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 supply voltage (v) d i s a b l e t i m e ( s ) 300 350 400 450 500 550 600 650 -60 -40 -20 0 20 40 60 80 100 120 140 r l = temperature (c) supply current (na)
isl28915 6 july 12, 2012 fn8343.0 figure 13. i bias+ vs temperature, v+, gnd = 2.5v figure 14. i bias- vs temperature, v+, gnd = 2.5v figure 15. i os vs temperature, v+, gnd = 2.5v figure 16. v os vs temperature, v+, gnd = 2.5v, v cm = 0v figure 17. cmrr vs temperature, v cm = 0.5v to 3.5, v+, gnd = 2.5v figure 18. v out high vs temperature, v+, gnd = 2.5v, r l = 10k typical performance curves (continued) -2 -1 0 1 2 3 4 -60 -40 -20 0 20 40 60 80 100 120 140 i b i a s + ( p a ) temperature (c) 0 1 2 3 4 5 6 -60 -40 -20 0 20 40 60 80 100 120 140 i b i a s - ( p a ) temperature (c) o f f s e t c u r r e n t ( p a ) temperature (c) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -60 -40 -20 0 20 40 60 80 100 120 140 50 70 90 110 130 150 170 190 210 230 250 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (c) o f f s e t v o l t a g e ( v ) 70 75 80 85 90 95 100 105 110 -60 -40 -20 0 20 40 60 80 100 120 140 c m r r ( db ) temperature (c) 4.980 4.982 4.984 4.986 4.988 4.990 4.992 4.994 4.996 4.998 5.000 -60 -40 -20 0 20 40 60 80 100 120 140 v ou t ( v ) temperature (c)
isl28915 7 july 12, 2012 fn8343.0 figure 19. v out low vs temperature, v+, gnd = 2.5v, r l = 10k figure 20. positive propagation delay vs temperature 50% to 50%, v+ = 5v figure 21. negative propagation delay vs temperature 50% to 50%, v+ = 5v figure 22. rise time vs temp erature 20% to 80%, v+ = 5v figure 23. fall time vs temp erature 20% to 80%, v+ = 5v typical performance curves (continued) 0 1 2 3 4 5 6 7 8 9 10 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (c) v o u t ( m v ) 100 110 120 130 140 150 160 170 180 -60 -40 -20 0 20 40 60 80 100 120 140 +propagation delay (s) temperature (c) 90 100 110 120 130 140 150 160 170 180 -60 -40 -20 0 20 40 60 80 100 120 140 -propagation delay (s) temperature (c) 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (c) rise delay (s) 7 8 9 10 11 12 13 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (c) fall delay (s)
isl28915 8 july 12, 2012 fn8343.0 applications information introduction the isl28915 is a cmos rail-to-rail input and output (rrio) nanopower comparator. this device is designed to operate from single supply (1.8v to 5.5v) and have an input common mode range that extends to the positive rail and to the negative supply rail for true rail-to-rail performance. the cmos output can swing within tens of millivolts to the rails. featuring worst case maximum supply current of only 900na, this comparator is ideally suited for solar and battery powered applications. input protection all input terminals have internal esd protection diodes to both positive and negative supply rail s, limiting the input voltage to within one diode beyond the supply rails. the isl28915 has a maximum input differential voltage that extends beyond the rails (v+ + 0.5v to gnd - 0.5v). rail-to-rail output a pair of complementary mosfet devices are used to achieve the rail-to-rail output swing. the nmos sinks current to swing the output in the negative directio n. the pmos sources current to swing the output in the positive direction. the isl28915 with a 10k ? load will typically swing to within 10mv of the positive supply rail and within 35mv of ground. break-before-make operation of the output the output circuit has a break-before-make response. this means that the p-channel turns off before the n-channel turns on during a high to low transition of the output (reference figure 24). likewise, the n-channel turns off before the p-channel turns on during a low to high transition. this results in different propagation delay times depending upon where the output load resistor is tied to. if the load resistor is tied to ground (figure 25a), then the propagatio n delay is controlled by the p-channel. for a high to low tr ansition, the propagation delay does not include the additional break-before-make time because the load resistor will pull the output low once the p-channel has turned off. during the low to high transition, however, if the load resistor is tied to ground, then the additi onal break-before-make time is added to the propagation delay time because the output won?t pull high until the p-channel turns on. if the load resistor is tied to v+ (figure 25b), then the propagation delay is controlled by the n-channel. for this condition, the additional delay time is added to the high to low transition because the output won?t pull low until the n-channel turns on. figures 4 through 7 show the differences in propagation delay depending upon where the load is tied. propagation delay the input to output propagation delay has a dependency on power supply voltage, overdrive and whether the output is sourcing or sinking current. figu res 4 and 5 show a decreasing time propagation delay vs supply voltage for the isl28915. the output break-before-make mechanis m results in a difference in propagation delay, depending on whether the output stage nmos and pmos are sourcing or sinking current. this delay difference is shown in the figures as a function of where the load is terminated (v+ or gnd) and also as a function of supply voltage. the dependence of prop agation delay as a function of power supply voltage and input overdrive (from 5mv to 1v) is shown in figures 6 and 7. propag ation delay is measured from the time the input signal reached 50% of its final value to the time the output reaches 50% of it s final value. rise and fall times are measured from the time the sign al is at 20% of its final value to the time it reaches 80% of the final value. enable feature the isl28915 in the 6 ld sot-23 package offers an en pin that enables the device when pulled high. the enable threshold is referenced to the gnd terminal an d has a level proportional to the total supply voltage (reference figu re 9 for en threshold vs supply voltage). the enable circuit has a delay time that changes as a function of supply voltage. figures 10 and 11 show the effect of supply voltage on the enable and disable times. the enable and disable delay is measured from the time the signal crosses the enable threshold to the time the output reaches 20% of its final value. for supply voltages less th an 3v, it is recommended that the user account for the increased enable/disable delay time. vout v+ p-channel n-channel p-ch on p-ch off n-ch off n-ch on n-ch off p-ch on figure 24. make-before-break action of the output stage isl28915 output stage break-before-make figure 25a. r l to gnd figure 25b. r l to v+ figure 25. connection of r l to gnd and v+ + - v out v+ r l + - v out v+ r l
isl28915 9 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com july 12, 2012 fn8343.0 for additional products, see www.intersil.com/product_tree in the disabled state (output in a high impedance state), the supply current is reduced to a typical of only 0.25na. by disabling the devices, multiple parts can be connected together as a mux. in this configuration, the outputs are tied together in parallel and a channel can be selected by the en pin. the en pin should never be left floating. the en pin should be connected directly to the v+ supply when not in use. proper layout maximizes performance to achieve the maximum performance of the high input impedance, care should be taken in the circuit board layout. the pc board surface must remain cl ean and free of moisture to avoid leakage currents between ad jacent traces. surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. when input leakage current is a concern, the use of guard rings around the comparator inputs will further reduce leakage currents. products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isl28915 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.com/reports/sear revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change july 16, 2012 fn8343.0 initial release
isl28915 10 july 12, 2012 fn8343.0 package outline drawing p6.064a 6 lead small outline transistor plastic package rev 0, 2/10 1.60 0.08-0.20 see detail x (0.60) 0-3 3 5 detail "x" side view typical recommended land pattern top view end view index area pin 1 seating plane gauge 0.450.1 (2 plcs) 10 typ 4 1.90 0.40 0.05 2.90 0.95 2.80 0.05-0.15 1.14 0.15 0.20 c a-b d m (1.20) (0.60) (0.95) (2.40) 0.10 c 1.45 max c b a d 3 3 0.20 c (1.90) 2x 0.15 c 2x d 0.15 c 2x a-b (0.25) h 64 5 5 13 2 plane dimension is exclusive of mold flash, protrusions or gate burrs. this dimension is measured at datum ?h?. package conforms to jedec mo-178aa. foot length is measured at reference to guage plane. dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. 3. 5. 4. 2. dimensions are in millimeters. 1. notes:


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